template <typename BuilderImpl>class WireTableBaseBuilder
Defined at line 510 of file fidling/gen/sdk/fidl/fuchsia.audio.device/fuchsia.audio.device/cpp/fidl/fuchsia.audio.device/cpp/wire_types.h
Public Methods
::fuchsia_audio_device::wire::RingBufferProperties Build ()Build and return the table. The builder should not be used after this.
bool has_valid_bits_per_sample ()void clear_valid_bits_per_sample ()Clears the valid_bits_per_sample field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
uint8_t & valid_bits_per_sample ()The number of bits (starting with the most significant) that are valid,
within each individual sample. This may be be smaller than the actual
sample size, in the case of an input ring buffer fed by an 18-bit ADC
for example. Any additional bits of precision should be ignored.
Required.
BuilderImpl & valid_bits_per_sample (uint8_t elem)The number of bits (starting with the most significant) that are valid,
within each individual sample. This may be be smaller than the actual
sample size, in the case of an input ring buffer fed by an 18-bit ADC
for example. Any additional bits of precision should be ignored.
Required.
bool has_turn_on_delay ()void clear_turn_on_delay ()Clears the turn_on_delay field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
int64_t & turn_on_delay ()The maximum delay until disabled channels become fully operational,
after calling `SetActiveChannels`. This is the worst-case duration when
reenabling all channels. The value must be non-negative.
Required.
BuilderImpl & turn_on_delay (Wrapper_Ignore_Me_< ::fidl::ObjectView<int64_t>> elem)The maximum delay until disabled channels become fully operational,
after calling `SetActiveChannels`. This is the worst-case duration when
reenabling all channels. The value must be non-negative.
Required.
Protected Methods
void WireTableBaseBuilder< ::fuchsia_audio_device::wire::RingBufferProperties, BuilderImpl> (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_audio_device::wire::RingBufferProperties>> && frame)