template <typename BuilderImpl>
class WireTableBaseBuilder
Defined at line 13641 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h
Public Methods
::fuchsia_sysmem2::wire::FormatCostEntry Build ()
Build and return the table. The builder should not be used after this.
bool has_key ()
void clear_key ()
Clears the key field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
::fuchsia_sysmem2::wire::FormatCostKey & key ()
Must be set. If two entries have logically equal key (after field
defaults are applied), the later entry will override the earlier entry.
BuilderImpl & key (Wrapper_Ignore_Me_< ::fidl::ObjectView< ::fuchsia_sysmem2::wire::FormatCostKey>> elem)
Must be set. If two entries have logically equal key (after field
defaults are applied), the later entry will override the earlier entry.
bool has_cost ()
void clear_cost ()
Clears the cost field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
float & cost ()
Must be set. Lower costs win, but see also FormatCostKey fields re.
filtering entries by format and usage bits first.
When two entries (each with format supported by all the participants of
a buffer collection) have different costs, the lower cost entry (and its
format) is chosen.
For non-test scenarios, only use cost values > 0.0 (typically at least
1.0 as of this comment), with 0.0 and negative values reserved for
testing.
BuilderImpl & cost (float elem)
Must be set. Lower costs win, but see also FormatCostKey fields re.
filtering entries by format and usage bits first.
When two entries (each with format supported by all the participants of
a buffer collection) have different costs, the lower cost entry (and its
format) is chosen.
For non-test scenarios, only use cost values > 0.0 (typically at least
1.0 as of this comment), with 0.0 and negative values reserved for
testing.
Protected Methods
void WireTableBaseBuilder< ::fuchsia_sysmem2::wire::FormatCostEntry, BuilderImpl> (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_sysmem2::wire::FormatCostEntry>> && frame)