template <typename BuilderImpl>

class WireTableBaseBuilder

Defined at line 2432 of file fidling/gen/sdk/fidl/fuchsia.net.tun/fuchsia.net.tun/cpp/fidl/fuchsia.net.tun/cpp/wire_types.h

Public Methods

::fuchsia_net_tun::wire::DevicePairConfig Build ()

Build and return the table. The builder should not be used after this.

bool has_base ()
void clear_base ()

Clears the base field.

This method should be used sparingly, such as only during tests, as it has

O(number_of_fields) complexity.

::fuchsia_net_tun::wire::BaseDeviceConfig & base ()

Base device configuration.

It not set, interpreted as an empty table.

BuilderImpl & base (Wrapper_Ignore_Me_< ::fidl::ObjectView< ::fuchsia_net_tun::wire::BaseDeviceConfig>> elem)

Base device configuration.

It not set, interpreted as an empty table.

bool has_fallible_transmit_left ()
void clear_fallible_transmit_left ()

Clears the fallible_transmit_left field.

This method should be used sparingly, such as only during tests, as it has

O(number_of_fields) complexity.

bool & fallible_transmit_left ()

If `true`, transmit buffers on the left end are dropped if no

receive buffers are available on the right end to receive it.

Otherwise, transmit buffers wait until a receive buffer is

available to copy them to.

It not set, interpreted as `false`.

BuilderImpl & fallible_transmit_left (bool elem)

If `true`, transmit buffers on the left end are dropped if no

receive buffers are available on the right end to receive it.

Otherwise, transmit buffers wait until a receive buffer is

available to copy them to.

It not set, interpreted as `false`.

bool has_fallible_transmit_right ()
void clear_fallible_transmit_right ()

Clears the fallible_transmit_right field.

This method should be used sparingly, such as only during tests, as it has

O(number_of_fields) complexity.

bool & fallible_transmit_right ()

Like `fallible_transmit_left` but allows writes to the right end

to be fallible.

It not set, interpreted as `false`.

BuilderImpl & fallible_transmit_right (bool elem)

Like `fallible_transmit_left` but allows writes to the right end

to be fallible.

It not set, interpreted as `false`.

Protected Methods

void WireTableBaseBuilder< ::fuchsia_net_tun::wire::DevicePairConfig, BuilderImpl> (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_net_tun::wire::DevicePairConfig>> && frame)

Records