template <>

class WireTableBuilder

Defined at line 728 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

Public Methods

template <typename First = ::fuchsia_hardware_audio_signalprocessing::wire::PlugState, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<::fuchsia_hardware_audio_signalprocessing::wire::PlugState>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_hardware_audio_signalprocessing::wire::DaiInterconnectElementState> & plug_state (First && first, Args &&... args_)

The plug state for this DAI interconnect.

Required.

Defined at line 743 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

template <typename First = int64_t, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<int64_t>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_hardware_audio_signalprocessing::wire::DaiInterconnectElementState> & external_delay (First && first, Args &&... args_)

The driver's best estimate of the external delay beyond this DAI endpoint, as the pipeline

is currently configured.

`external_delay` must be taken into account by the client when determining the requirements

for minimum lead time (during playback) and minimum capture delay (during capture).

If not included, `external_delay` is unknown; the client may treat it however it chooses

(e.g. consider it zero or some other duration, autodetect it, etc).

Optional. If specified, must be non-negative.

Defined at line 765 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

Friends

template <>

class DaiInterconnectElementState