class WireTableBuilder

template <typename First = uint64_t, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<uint64_t>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_process_explorer::wire::Mapping> & vmo_koid (First && first, Args &&... args_)

Defined at line 1928 of file fidling/gen/sdk/fidl/fuchsia.process.explorer/fuchsia.process.explorer/cpp/fidl/fuchsia.process.explorer/cpp/wire_types.h

template <typename First = uint64_t, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<uint64_t>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_process_explorer::wire::Mapping> & vmo_offset (First && first, Args &&... args_)

Defined at line 1940 of file fidling/gen/sdk/fidl/fuchsia.process.explorer/fuchsia.process.explorer/cpp/fidl/fuchsia.process.explorer/cpp/wire_types.h

template <typename First = uint64_t, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<uint64_t>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_process_explorer::wire::Mapping> & committed_pages (First && first, Args &&... args_)

Defined at line 1952 of file fidling/gen/sdk/fidl/fuchsia.process.explorer/fuchsia.process.explorer/cpp/fidl/fuchsia.process.explorer/cpp/wire_types.h

template <>

class Mapping