class WireTableBuilder

template <typename First = ::fidl::StringView, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<::fidl::StringView>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_process_explorer::wire::Vmap> & name (First && first, Args &&... args_)

Defined at line 2264 of file fidling/gen/sdk/fidl/fuchsia.process.explorer/fuchsia.process.explorer/cpp/fidl/fuchsia.process.explorer/cpp/wire_types.h

template <typename First = uint64_t, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<uint64_t>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_process_explorer::wire::Vmap> & base_address (First && first, Args &&... args_)

Defined at line 2276 of file fidling/gen/sdk/fidl/fuchsia.process.explorer/fuchsia.process.explorer/cpp/fidl/fuchsia.process.explorer/cpp/wire_types.h

template <typename First = uint64_t, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<uint64_t>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_process_explorer::wire::Vmap> & size (First && first, Args &&... args_)

Defined at line 2288 of file fidling/gen/sdk/fidl/fuchsia.process.explorer/fuchsia.process.explorer/cpp/fidl/fuchsia.process.explorer/cpp/wire_types.h

template <typename First = uint64_t, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<uint64_t>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_process_explorer::wire::Vmap> & depth (First && first, Args &&... args_)

Defined at line 2300 of file fidling/gen/sdk/fidl/fuchsia.process.explorer/fuchsia.process.explorer/cpp/fidl/fuchsia.process.explorer/cpp/wire_types.h

template <typename First = ::fuchsia_process_explorer::wire::Mapping, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<::fuchsia_process_explorer::wire::Mapping>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_process_explorer::wire::Vmap> & mapping (First && first, Args &&... args_)

Defined at line 2313 of file fidling/gen/sdk/fidl/fuchsia.process.explorer/fuchsia.process.explorer/cpp/fidl/fuchsia.process.explorer/cpp/wire_types.h

template <>

class Vmap