class WireTableBuilder

template <>

class WireTableBuilder

Defined at line 2175 of file fidling/gen/sdk/fidl/fuchsia.virtualaudio/fuchsia.virtualaudio/cpp/fidl/fuchsia.virtualaudio/cpp/wire_types.h

Public Methods

template <typename First = ::fidl::VectorView<::fuchsia_virtualaudio::wire::CompositeRingBuffer>, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<::fidl::VectorView<::fuchsia_virtualaudio::wire::CompositeRingBuffer>>>, int> = 0>
::fidl::WireTableBuilder< ::fuchsia_virtualaudio::wire::Composite> & ring_buffers (First && first, Args &&... args_)

Ring buffers configuration.

Required.

Defined at line 2190 of file fidling/gen/sdk/fidl/fuchsia.virtualaudio/fuchsia.virtualaudio/cpp/fidl/fuchsia.virtualaudio/cpp/wire_types.h

template <typename First = ::fidl::VectorView<::fuchsia_virtualaudio::wire::CompositeDaiInterconnect>, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<::fidl::VectorView<::fuchsia_virtualaudio::wire::CompositeDaiInterconnect>>>, int> = 0>
::fidl::WireTableBuilder< ::fuchsia_virtualaudio::wire::Composite> & dai_interconnects (First && first, Args &&... args_)

DAI interconnects configurations.

Required.

Defined at line 2205 of file fidling/gen/sdk/fidl/fuchsia.virtualaudio/fuchsia.virtualaudio/cpp/fidl/fuchsia.virtualaudio/cpp/wire_types.h

template <typename First = ::fuchsia_virtualaudio::wire::ClockProperties, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<::fuchsia_virtualaudio::wire::ClockProperties>>, int> = 0>
::fidl::WireTableBuilder< ::fuchsia_virtualaudio::wire::Composite> & clock_properties (First && first, Args &&... args_)

Configuration for the device's clock.

Required.

Defined at line 2220 of file fidling/gen/sdk/fidl/fuchsia.virtualaudio/fuchsia.virtualaudio/cpp/fidl/fuchsia.virtualaudio/cpp/wire_types.h

template <typename First = ::fidl::VectorView<::fuchsia_hardware_audio_signalprocessing::wire::Topology>, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<::fidl::VectorView<::fuchsia_hardware_audio_signalprocessing::wire::Topology>>>, int> = 0>
::fidl::WireTableBuilder< ::fuchsia_virtualaudio::wire::Composite> & topologies (First && first, Args &&... args_)

Topologies supported via the signalprocessing API.

Optional.

Defined at line 2235 of file fidling/gen/sdk/fidl/fuchsia.virtualaudio/fuchsia.virtualaudio/cpp/fidl/fuchsia.virtualaudio/cpp/wire_types.h

Friends

template <>
class Composite