class WireTableBuilder

template <typename First = uint64_t, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<uint64_t>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_cpu_profiler::wire::SessionStopResponse> & samples_collected (First && first, Args &&... args_)

Defined at line 2076 of file fidling/gen/sdk/fidl/fuchsia.cpu.profiler/fuchsia.cpu.profiler/cpp/fidl/fuchsia.cpu.profiler/cpp/wire_types.h

template <typename First = uint64_t, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<uint64_t>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_cpu_profiler::wire::SessionStopResponse> & mean_sample_time (First && first, Args &&... args_)

Defined at line 2088 of file fidling/gen/sdk/fidl/fuchsia.cpu.profiler/fuchsia.cpu.profiler/cpp/fidl/fuchsia.cpu.profiler/cpp/wire_types.h

template <typename First = uint64_t, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<uint64_t>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_cpu_profiler::wire::SessionStopResponse> & median_sample_time (First && first, Args &&... args_)

Defined at line 2100 of file fidling/gen/sdk/fidl/fuchsia.cpu.profiler/fuchsia.cpu.profiler/cpp/fidl/fuchsia.cpu.profiler/cpp/wire_types.h

template <typename First = uint64_t, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<uint64_t>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_cpu_profiler::wire::SessionStopResponse> & min_sample_time (First && first, Args &&... args_)

Defined at line 2112 of file fidling/gen/sdk/fidl/fuchsia.cpu.profiler/fuchsia.cpu.profiler/cpp/fidl/fuchsia.cpu.profiler/cpp/wire_types.h

template <typename First = uint64_t, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<uint64_t>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_cpu_profiler::wire::SessionStopResponse> & max_sample_time (First && first, Args &&... args_)

Defined at line 2124 of file fidling/gen/sdk/fidl/fuchsia.cpu.profiler/fuchsia.cpu.profiler/cpp/fidl/fuchsia.cpu.profiler/cpp/wire_types.h

template <typename First = ::fidl::VectorView<uint64_t>, typename... Args, std::enable_if_t<!std::is_same_v<cpp20::remove_cvref_t<First>, fidl::ObjectView<::fidl::VectorView<uint64_t>>>, int> = 0>

::fidl::WireTableBuilder< ::fuchsia_cpu_profiler::wire::SessionStopResponse> & missing_process_mappings (First && first, Args &&... args_)

Defined at line 2136 of file fidling/gen/sdk/fidl/fuchsia.cpu.profiler/fuchsia.cpu.profiler/cpp/fidl/fuchsia.cpu.profiler/cpp/wire_types.h

template <>

class SessionStopResponse