struct DphyInterfaceConfig

Defined at line 53 of file ../../src/graphics/display/lib/designware-dsi/dphy-interface-config.h

The DesignWare MIPI DSI Host Controller connects to the MIPI D-PHY physical

layer over the PHY-Protocol Interface (PPI) for signal output.

Configures the output interface and timers so that the output signal format

and timings matches the D-PHY transmitter.

Public Members

int data_lane_count

bool clock_lane_mode_automatic_control_enabled

int64_t high_speed_mode_clock_lane_frequency_hz

int64_t escape_mode_clock_lane_frequency_hz

int32_t max_data_lane_hs_to_lp_transition_duration_lane_byte_clock_cycles

int32_t max_data_lane_lp_to_hs_transition_duration_lane_byte_clock_cycles

int32_t max_clock_lane_hs_to_lp_transition_duration_lane_byte_clock_cycles

int32_t max_clock_lane_lp_to_hs_transition_duration_lane_byte_clock_cycles

int64_t high_speed_mode_data_lane_bits_per_second ()

Defined at line 134 of file ../../src/graphics/display/lib/designware-dsi/dphy-interface-config.h

int64_t escape_mode_data_lane_bits_per_second ()

Defined at line 139 of file ../../src/graphics/display/lib/designware-dsi/dphy-interface-config.h

int64_t high_speed_mode_data_lane_bytes_per_second ()

Defined at line 144 of file ../../src/graphics/display/lib/designware-dsi/dphy-interface-config.h

int64_t escape_mode_data_lane_bytes_per_second ()

Defined at line 148 of file ../../src/graphics/display/lib/designware-dsi/dphy-interface-config.h

Picoseconds unit_interval ()

The Unit Interval (UI) is defined as the time equal to the duration of any

High Speed (HS) state on the Clock Lane. It equals to the duration to

transmit a bit on the data line on High Speed mode.

D-PHY spec, Section 2.4 "Acronyms", page 6.

D-PHY spec, Section 10.1 "High-Speed Clock Timing", Figure 86 "DDR Clock

Definition", page 143.

Defined at line 160 of file ../../src/graphics/display/lib/designware-dsi/dphy-interface-config.h

Picoseconds lane_byte_clock_period ()

The duration to transmit a byte (8 bits) on the data line on High Speed

mode.

Also known as "lanebyteclk" in the DSI Host Databook and User Guide.

Defined at line 168 of file ../../src/graphics/display/lib/designware-dsi/dphy-interface-config.h

Picoseconds max_data_lane_hs_to_lp_transition_duration ()

Defined at line 173 of file ../../src/graphics/display/lib/designware-dsi/dphy-interface-config.h

Picoseconds max_data_lane_lp_to_hs_transition_duration ()

Defined at line 177 of file ../../src/graphics/display/lib/designware-dsi/dphy-interface-config.h

Picoseconds max_clock_lane_hs_to_lp_transition_duration ()

Defined at line 181 of file ../../src/graphics/display/lib/designware-dsi/dphy-interface-config.h

Picoseconds max_clock_lane_lp_to_hs_transition_duration ()

Defined at line 185 of file ../../src/graphics/display/lib/designware-dsi/dphy-interface-config.h

bool IsValid ()

Defined at line 193 of file ../../src/graphics/display/lib/designware-dsi/dphy-interface-config.h