class MiFlush

class MiFlush

Defined at line 94 of file ../../src/graphics/drivers/msd-intel-gen/src/instructions.h

intel-gfx-prm-osrc-kbl-vol02a-commandreference-instructions.pdf p.996

"HW implicitly detects the Data size to be Qword or Dword to be

written to memory based on the command dword length programmed"

Note: TLB invalidations are implicit on every flush sync since Skylake

(GFX_MODE bit 13 "Flush TLB invalidation Mode", from Broadwell spec, removed).

This is also validated empirically (test_hw_exec.cc)

Public Members

static const uint32_t kDwordCount
static const uint32_t kCommandType
static const uint32_t kCommandOpcode
static const uint32_t kPostSyncWriteImmediateBit
static const uint32_t kAddressSpaceGlobalGttBit

Public Methods

void write (magma::InstructionWriter * writer, uint32_t sequence_number, AddressSpaceType address_space_type, uint64_t gpu_addr)

Defined at line 102 of file ../../src/graphics/drivers/msd-intel-gen/src/instructions.h