class MiPipeControl

class MiPipeControl

Defined at line 119 of file ../../src/graphics/drivers/msd-intel-gen/src/instructions.h

intel-gfx-prm-osrc-skl-vol02a-commandreference-instructions.pdf pp.1057

Note: TLB invalidations are implicit on every flush sync since Skylake

(GFX_MODE bit 13 "Flush TLB invalidation Mode", from Broadwell spec, removed).

This is also validated empirically (test_hw_exec.cc)

Public Members

static const uint32_t kDwordCount
static const uint32_t kCommandType
static const uint32_t kCommandSubType
static const uint32_t k3dCommandOpcode
static const uint32_t k3dCommandSubOpcode
static const uint32_t kDcFlushEnableBit
static const uint32_t kIndirectStatePointersDisableBit
static const uint32_t kPostSyncWriteImmediateBit
static const uint32_t kGenericMediaStateClearBit
static const uint32_t kCommandStreamerStallEnableBit
static const uint32_t kAddressSpaceGlobalGttBit
static const uint32_t kAddressSpaceGen9ClearEuBit

Public Methods

void write (magma::InstructionWriter * writer, uint32_t sequence_number, uint64_t gpu_addr, uint32_t flags)

Defined at line 135 of file ../../src/graphics/drivers/msd-intel-gen/src/instructions.h